1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices and more particularly to a method of planarizing a semiconductor structure during manufacture by backfilling etched depressions between raised features with a self-aligning, lift-off layer of dielectric material which is then selectively removed from the features and covered with a self-aligning polymer material. The invention further relates to a method of improving the isoplanar characteristics of metallic interconnection layers in multi-layered semiconductor structures through polyimide deposition on a self-aligned backfilled dielectric layer.
2. Background of Related Art
There is a continuing need to develop integrated circuits and components that operate at higher frequencies or speeds, with reduced power and within smaller volumes. These requirements or design goals place a greater emphasis on development of increased component integration and packing density, which results in decreased feature sizes, increased interconnection complexity, and use of new or specialized materials.
However, increased packing densities and decreased feature sizes, especially for small aspect ratios, width to height, lead to surface topologies that create problems for device performance and survivability. Substantial variations in feature height, topography or morphology leads to stress in subsequently deposited layers or materials at corners or height transitions. This stress results in microcracking and other material failures. At the same time, significant height variations in one layer makes precise control of the dimensions of subsequent material layers difficult. Imprecise material deposition increases problems with breakdown and parasitics between layers or features which must be minimized while maintaining operational integrity.
Therefore, planarization techniques are generally employed to increase yield and decrease failure rates in newer circuits and to obtain desired operating characteristics. Planarization is very important for controlling variations in device performance and yield and more advanced circuit requirements place further demands on planarization techniques.
A variety of techniques have been employed in an attempt to ameliorate surface morphology problems. One technique is the application or deposition of a finishing layer across the top of various spaced-apart features comprising a photoresist or polymer material. A re-flow process is then used to spread the material to create a more uniform surface. Unfortunately, while such finishing layer material fills narrow trenches and shallow depressions, wider (and deeper) expanses, such as typically found on a mesa populated layer, tend to result in corresponding valleys and depressions in the polymer layer. Excessively large amounts of polymer are required to compensate for the effect of larger feature variations. Since very thin intermediate material layers are desired for proper via formation, this technique has proven unacceptable.
Another technique is to apply a layer of dielectric material over selected features and heat it to cause it to re-flow over uppermost surfaces and form a planar upper surface. Unfortunately, this re-flow technique requires higher temperatures than are generally compatible or acceptable with many underlying processes or devices. This technique also requires more material and greater thickness for large depressions than desired.
What is needed is a method of planarizing selected layers of a semiconductor structure with a very thin layer of material which is highly compatible with many lower temperature processes and is preferably useful with multi-layered structures.